> I'm thinking the former, though it's whatever is necessary to make the emulator
> behave the same way as the real hardware. I don't think it should be necessary to
> interrupt instructions on *any* cycle (definitely not in the IRQ sense), but there
> may be some instructions that have multiple time-sensitive externally observable
> effects - e.g. a word access to CGA RAM will have two separate wait states, each
> synchronizing with the CGA's LCLK and possibly generating a flake of snow.
I don't know if it's specifically the PC or some other system using an 8088/8086, but I seem to recall hearing about a system in MESS that's finicky because the hardware's floppy controller can actually halt the CPU mid-instruction. For something like that, you need to actually have per-cycle emulation rather than just instructions with correct cycle counts. It's kind of scary how some companies designed their hardware.