> Sounds like the equivalent on the PC to the "+IO CH RDY" line on the ISA bus. A
> peripherial can pull this low to suspend one of the phases of a bus access cycle,
> introducing wait states. That's not quite the same as interrupting the CPU on an
> arbitrary cycle, though - the execution unit can keep on running during these wait
> states, and the bus interface unit can only be suspended in one of its phases.
From an emulation point of view, it's roughly equivalent. What hardware does usually is stop the cpu on a bus access. Since instructions can do more than one bus access (the 68000 can reach around 68 I think) it means suspending the execution in the middle of an instruction. From a cpu emulation software point of view, there are four possible points to stop execution: almost never (static recompilers), at a branch (dynamic recompilers), at the end of an instruction (traditional cpu cores) or at any time (cycle-precise cpu cores). Each level increases overhead and the amount of state to track, but also increases timing precision. Any time vs. at a bus access is pretty impossible to distinguish externally, and in practice cycle-precise cpu cores are an hybrid of the two.